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Adaptive Sub-Row Management in Large-Capacity Memory Devices
Row buffers play an important role in large-capacity memory devices because they behave like an extra level of cache and efficiently hide a slow memory cell operation time by accessing large amount of data at a time. The size of single row buffer is up to few KBs, and thus each activate/precharge operation involves significant amount of energy proportional to the size of row. This paper focuses on optimizing the performance and energy consumption of row activations by aggressively exploiting sub-row architecture. Conventional sub-row architectures may result in degrading the performance if the sub-row size is less than a certain value in which the inefficient row activation and buffer management happen frequently. In order to mitigate this performance degradation in sub-row architecture, we adaptively control the sub-row activation by tracking the memory access patterns with almost negligible implementation overhead. The proposed adaptive sub-row activation management enables us to aggressively reduce the sub-row size without severe performance degradation. Extensive simulation with traces from real applications running on a full-system simulator of multicore system demonstrates up to 26.7% energy-delay product, as compare to the conventional sub-row architecture.
DRAM, row buffer, prefetch, sub-row architecture, Computer systems organization~Processors and memory architectures, Hardware~Memory and dense storage
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