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EEPROM-SRAM Hybrid Non-Volatile Counter Architecture and Lifetime Maximization Considering Limited Energy and Write Cycles

The-Nghia Nguyen, Ngoc-Dung Nguyen, Donghwa Shin

Abstract



A non-volatile counter is a device designed to count and record the number of specific events without an external power supply. The conventional non-volatile counter has been implemented with volatile memory using a battery backup, or with non-volatile memory, such as embedded flash or electrically erasable programmable read-only memory. Both have drawbacks related to the lifespan of the product owing to the limited lifetime of the battery or to the limited endurance of non-volatile memory cells. In this paper, we propose a hybrid non-volatile architecture combining the advantages of battery-assisted volatile memory and non-volatile memory to extend the lifetime of a non-volatile counter with lower costs in design and higher reliability in usage. To verify the effectiveness of the proposed method, we analyze its performance with various parameters of non-volatile memory. The experimental results show that the proposed hybrid-architecture non-volatile counter can extend the counter’s lifetime by between 1.7% and 24.0%, in comparison with a battery-assisted volatile memory-based implementation.

Keywords


Counter, non-volatile, battery backup, EEPROM, SRAM

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