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Robust FPGA Hardware Architecture of DPSO Multilevel Image Segmentation



The segmentation presents a fundamental step in every image treatment. It is applied to prepare image for detection, classification and recognition. Also, it is widely used in diverse of fields such as robotics, medical imaging and visions. Thus, it is very important for researchers to develop a new technique to succeed the segmentation stage. In this paper, we proposed a hardware architecture based on Darwinian Particle Swarm Optimization (DPSO) algorithm for multilevel image segmentation using Xilinx System Generator (XSG) tool implemented on Programmable Field Gate Array (FPGA) type Virtex V of XILINX. The integration enters the two tools, Simulink of MATLAB and XSG offers a graphic interface making the visualization of the inputs/outputs. Thus, experimental results can be shown using this tool. The performance of the proposed technique is validated and demonstrated using a set of Benchmarks images.


XSG, FPGA, algorithm DPSO, multilevel segmentation

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