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Design of Square Root Carry Select Adder to Achieve Low Power Consumption
Abstract
Carry Select adder (CSLA) is known to be the fastest adder among the Conventional adder structures.An efficient carry select adder (CSLA) is designed to eliminate the redundant logic operation in the conventional CSLA.In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum. Due to the small carry- output delay, the proposed CSLA design is a good applicant for square-root CSLA. Thus the proposed CSLA design involves significantly less area and low power than the recently proposed conventional CSLA. The reason for area reduction is that, the quantity of logic gates used to design a proposed scheme is less than the number of logic gates used for a conventional CSLA.
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