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An Unified Architecture for Affine Transformations of 2D Images for Real Time Applications
Image registration is widely used in medical imaging, remote sensing, computer vision etc. Affine transformation is one of the important operations in image registration. In medical applications, images of similar or differing modalities often need to be aligned in real time during image guided therapy systems. For realizing image registration in real time, faster implementation of affine transform is imperative. Affine transform consists of four basic operations such as rotation, shearing, scaling and translation. This paper presents an unified architecture for implementation of 2D affine transformations in real time using our previously proposed algorithm named ATPR (acronym for Affine Transform by Pixel Replication). By exploiting the replication of the pixel location in an image, the proposed ATPR algorithm helps in reducing the number of matrix multiplication to half compared to that of the conventional method. The ATPR algorithm is initially verified using MATLAB and then mapped to a pipelined architecture. The detailed architecture is coded using Verilog hardware description language (Verilog HDL) and implemented using Xilinx field programmable gate array (FPGA). The affine transform core is able to operate at a maximum frequency of 320MHz with Xilinx VirtexIIP FPGA. The parallelism of the proposed algorithm and pipelining of the architecture help in transforming a gray scale image of size. The proposed technique is able to achieve significant speedup at the cost of marginal increase in hardware while maintaining the image quality.
Affine transform, ATPR algorithm, FPGA, Parallel processing, Image registration.
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