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Fast SAD Algorithm of HEVC Video Encoder on Two Successive GPU Generations

R. Khemiri, M. Chouchene, H. Bahri, F. E. Sayadi, H. Kibeya, M. Atri, N. Masmoudi

Abstract


Reducing the Sum of Absolute Differences (SAD) computational time, reduces the motion estimation (ME) time, which leads to the decrease of all the High-Efficiency Video Coding (HEVC) time. This paper proposes two parallel implementation of the SAD algorithm of the HEVC Motion Estimation (ME), on Fermi and Kepler GPUs (Graphic Processing Unit) generations. Both implementations are computed with Compute Unified Device Architecture (CUDA). A comparison of the obtained results, on those two successive GPU generations, are given and discussed, for some test blocks, from 4x4 to 64x64.The investigational results show that the speedup reaches a maximum at the biggest block size used for HEVC encoder, regardless the system GPU card used. The GPU performances for 64x64-block size are enhanced, compared to the results obtained on CPU, by around 50% for the Fermi GPU system and by 25% for the Kepler one. By comparing the results on GPU, for each architectures, we concluded that the GPU frequency affects the execution time deeply even more than the compute capability (CC) or the number of threads disposed in the card, i.e., regardless the processor generation used.

Keywords


HEVC, Motion Estimation, SAD, Fermi GPU system, Kepler GPU system, CUDA

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